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ILX532A
7500-pixel CCD Linear Sensor (B/W)
Description The ILX532A is a reduction type CCD linear sensor developed for high resolution copiers. This sensor reads A3-size documents at a density of 600DPI, at high speed. Features * Number of effective pixels: 7500 pixels * Pixel size: 7m x 7m (7m pitch) * Clamp circuit are on-chip * Signal output phase of two-output simultaneous-output (alternate-output is available) * Ultra high sensitivity/Ultra low lag * Max Data Rate: 40MHz * Single 12V power supply * Input Clock Pulse: CMOS 5V drive * Package: 28 pin Cer-DIP (400mil) Absolute Maximum Ratings * Supply voltage VDD 15 * Operating temperature -10 to +60 * Storage temperature -30 to +80 Pin Configuration (Top View)
CLP-ODD RS-ODD LH-ODD GND VOUT-ODD VGG NC NC 2-ODD 1 2 3 4 5 6 7 8 9 1 28 CLP-EVEN 27 RS-EVEN 26 LH-EVEN 25 VDD
CLP-EVEN RS-EVEN LH-EVEN 26
28 pin DIP (Cer-DIP)
Block Diagram
ROG pulse generator
VDD
2-EVEN 1-EVEN
CCD analog shift register
CCD analog shift register
Read out gate
Read out gate
VDD
25
23 VDD 22 NC 21 NC 20 2-EVEN 19 GND 18 1-EVEN 17 VDD 7500 16 GND 15 NC
3 Output amplifier Output amplifier 2 VOUT-EVEN 24 6 VGG VOUT-ODD 5 4 1
24 VOUT-EVEN
1-ODD 10 VDD 11 ROG 12 NC 13 NC 14
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
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E98344-PS
GND CLP-ODD
28
RS-ODD
27
LH-ODD
GND
VDD
23
16
2-ODD 1-ODD VDD
17
18
20
9
10
11 S7499 S7500 D75 D74 S1 S2 D25 D26
D94
V C C
ROG
GND
19
12
ILX532A
Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Symbol CLP-ODD RS-ODD LH-ODD GND VOUT-ODD VGG NC NC 2-ODD 1-ODD VDD ROG NC NC Description Clock pulse input (odd pixel) Clock pulse input (odd pixel) Clock pulse input (odd pixel) GND Signal out (odd pixel) Output circuit gate bias NC NC Clock pulse input (odd pixel) Clock pulse input (odd pixel) 12V power supply Readout gate clock pulse input NC NC Pin No. 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Symbol NC GND VDD 1-EVEN GND 2-EVEN NC NC VDD VOUT-EVEN VDD LH-EVEN RS-EVEN CLP-EVEN NC GND 12V power supply Clock pulse input (even pixel) GND Clock pulse input (even pixel) NC NC 12V power supply Signal out (even pixel) 12V power supply Clock pulse input (even pixel) Clock pulse input (even pixel) Clock pulse input (even pixel) Description
Recommended Supply Voltage Item VDD Min. 11.4 Typ. 12 Max. 12.6 Unit V
Clock Characteristics Item Input capacity of 11, 21 Input capacity of LH1 Input capacity of RS1 Input capacity of CLP1 Input capacity of ROG Symbol C1, C2 CLH CRS CCLP CROG Min. -- -- -- -- -- Typ. 500 10 10 10 10 Max. -- -- -- -- -- Unit pF pF pF pF pF
1 It indicates that 1-ODD, 1-EVEN as 1, 2-ODD, 2-EVEN as 2, LH-ODD, LH-EVEN as LH, RS-ODD, RS-EVEN as RS, CLP-ODD, CLP-EVEN as CLP. Clock Frequency Symbol 1, 2, LH, RS, CLP Data rate f1, f2, fLH, fRS, fCLP fR Min. -- -- Typ. 1 2 Max. 20 40 Unit MHz MHz
Input Clock Pulse Voltage Condition Min. 1, 2, LH, RS, CLP, ROG pulse voltage Low level High level -2- -- 4.75 Typ. 0 5.0 Max. 0.1 5.25 Unit V V
ILX532A
Electrooptical Characteristics (Note 1) (Ta = 25C, VDD = 12V, fR = 2MHz, Input clock = 5Vp-p, Light source = 3200K, IR cut filter CM-500S (t = 1.0mm)) Item Sensitivity 1 Sensitivity 2 Sensitivity nonuniformity Saturation output voltage Saturation exposure Register imbalance Dark voltage average Dark signal nonuniformity Image lag Supply current Total transfer efficiency Output impedance Offset level Symbol R1 R2 PRNU VSAT SE RI VDRK DSNU IL IVDD TTE Zo VOS Min. 8.2 -- -- 1.8 0.13 -- -- -- -- -- 92 -- -- Typ. 11 25.1 4 2.5 0.23 1 0.3 0.6 0.02 30 98 150 6.5 Max. 13.8 -- 10 -- -- 7 2.0 5.0 -- 60 -- -- -- Unit V/(lx * s) V/(lx * s) % V lx * s % mV mV % mA % V Remarks Note 2 Note 3 Note 4 Note 5 Note 6 Note 7 Note 8 Note 9 Note 10 -- -- -- Note 11
Notes) 1. In accordance with the given electrooptical characteristics, the even black level is defined as the average value of D6, D8, to D24. The odd black level is defined as the average value of D5, D7, to D23. 2. For the sensitivity test light is applied with a uniform intensity of illumination. 3. W lamp (2854K) 4. PRNU is defined as indicated below. Ray incidence conditions are the same as for Note 2. VOUT = 500mV (Typ.) PRNU = (VMAX - VMIN)/2 VAVE x 100 [%]
5. 6. 7.
The maximum output of each odd and even pixels is set to VMAX, the minimum output to VMIN and the average output to VAVE. Use below the minimum value of the saturation output voltage. Saturation exposure is defined as follows. RI is defined as indicated bellow. RI = SE = VSAT R1
VOUT = 500mV (Typ.)
(
| VODD-AVE - VEVEN-AVE | x 100 [%] VODD-AVE + VEVEN-AVE 2
)
Where average of odd pixels output is set to VODD-AVE, even pixels to VEVEN-AVE. Optical signal accumulated time int stands at 10ms. The difference between the maximum and average values of the dark output voltage is calculated for even and odd respectively. The larger value is defined as the dark signal nonuniformity. Optical signal accumulated time int stands at 10ms. 10. VOUT = 500mV (Typ.) 11. VOS is defined as indicated below. 8. 9.
VOUT
VOS GND
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Clock Timing Chart 1 (simultaneous output)
ROG
1 2 3 3797 D23 D25 D27 D69 D71 D73 S1 S3 S7495 S7497 S7499 D75 D77 D79 D81 D83 D24 D26 D28 D70 D72 D74 S2 S4 S7496 S7498 S7500 D76 D78 D80 D82 D84
5
0
1-ODD 1-EVEN 5 LH-ODD 0 LH-EVEN
2-ODD 5 2-EVEN 0
RS-ODD 5 RS-EVEN 0
D1
D3
D5
VOUT-ODD
D2
D4
D6
VOUT-EVEN
Optical black (48 pixels) Dummy signal (74 pixels) 1-line output period (7594 pixels)
Note) The transfer pulses (1, 2, LH) must have more than 3797 cycles.
D94
D93
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CLP-ODD 5 CLP-EVEN 0
ILX532A
ILX532A
Clock Timing Chart 2
t4 t5
ROG t2 t6 1 LH t7
t1
t3
2
Clock Timing Chart 3
t7 1 LH t6
2 t10 t9 RS t8 t11
t14 CLP t13 t12
t15
t16 VOUT
t17
Clock timing of 1, 2, LH, RS, CLP and VOUT at odd or even are the same as timing chart 3 in the case of alternate output.
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ILX532A
Clock Timing Chart 4
Cross point 1 and 2 1 5V
1.5V (Min.) 2 0V
1.5V (Min.)
Cross point LH and 2 2 5V
2.0V (Min.) LH 0V
1.5V (Min.)
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Clock Timing Chart 5 (alternate output1)
ROG
1 2 3 3797 D23 D25 D27 D69 D71 D73 S1 S3 S7495 S7497 S7499 D75 D77 D79 D81 D83 D24 D26 D28 D70 D72 D74 S2 S4 S7496 S7498 S7500 D76 D78 D80 D82 D84 D93 D94
5
0
1-ODD 5 LH-ODD 0
2-ODD
5
0
1-EVEN 5 LH-EVEN 0
2-EVEN
5
0
RS-ODD
5
0
D1
D3 D2 D4
VOUT-ODD
RS-EVEN
5
CLP-EVEN
0 5
0
D6
VOUT-EVEN Optical black (48 pixels) Dummy signal (74 pixels)
D5
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1-line output period (7594 pixels)
CLP-ODD
5
0
ILX532A
Note) The transfer pulses (1, 2, LH) must have more than 3797 cycles. 1 Alternate output is available by making 1-EVEN, 2-EVEN, LH-EVEN, RS-EVEN, CLP-EVEN delayed to 1-ODD, 2-ODD, LH-ODD, RS-ODD, CLP-ODD for half a cycle.
ILX532A
Clock Pulse Recommended Timing Item ROG, 1 pulse timing ROG pulse high level period ROG, 1 pulse timing ROG pulse rise time ROG pulse fall time 1 pulse rise time/2 pulse fall time 1 pulse fall time/2 pulse rise time RS pulse high level period RS, CLP pulse timing RS pulse rise time RS pulse fall time CLP pulse high level period CLP, LH pulse timing CLP pulse rise time CL pulse fall time Signal output delay time Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 Min. 50 1000 1000 0 0 0 0 10 10 0 0 10 5 0 0 -- -- Typ. 100 1500 1500 5 5 20 20 2001 2001 10 10 2001 501 10 10 8 15 Max. -- -- -- 10 10 60 60 -- -- 30 30 -- -- 30 30 -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
1 These timing is the recommended condition under f1 = 1MHz.
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Application Circuit1
5.1k VOUT-EVEN Tr1 100
28 25 NC NC VDD VDD GND VDD 2-EVEN VOUT-EVEN 1-EVEN GND NC 13 14 12V 2 Tr1 IC1 2 47F 16V 0.1F NC IC1: 74AC04 Tr1: 2SC2785 NC 19 18 LH-EVEN
27
26
24
23
22 21 20 17 16 15
CLP-ODD CLP-EVEN
RS-ODD LH-ODD GND
RS-EVEN
VOUT-ODD VGG NC
NC
2-ODD
1-ODD VDD 11 12 ROG
1 0.1F
2
3
4 7 9
5
6
8
10
100
100
100 IC1 VOUT-ODD 5.1k 2 1
100
CLP RS LH
1 Data rate fR = 2MHz.
ILX532A
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
ROG
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ILX532A
Example of Representative Characteristics (VDD = 12V, Ta = 25C)
Spectral sensitivity characteristics (Standard characteristics)
1.0
0.8 Relative sensitivity
0.6
0.4
0.2
0 400
500
600
700 Wavelength [nm]
800
900
1000
Dark signal output temperature characteristics (Standard characteristics)
Integration time output voltage characteristics (Standard characteristics)
10 5 Output voltage rate Output voltage rate 0 10 20 30 40 50 60 1
1 0.5
0.5
0.1
0.1
1
5 int - integration time [ms]
10
Ta - Ambient temperature [C]
Offset level vs. VDD characteristics (Standard characteristics)
12 Ta = 25C 10 Vos - Offset level [V] Vos - Offset level [V]
Offset level vs. Temperature characteristics (Standard characteristics)
12
10
8
8
6
6
4
Vos VDD
4
0.6 2
Vos Ta
-2mV/C
2
0 11.4
12.0 VDD [V]
12.6
0
0
10
20
30
40
50
60
Ta - Ambient temperature [C]
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ILX532A
Notes of Handling 1) Static charge prevention CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following protective measures. a) Either handle bare handed or use non chargeable gloves, clothes or material. Also use conductive shoes. b) When handling directly use an earth band. c) Install a conductive mat on the floor or working table to prevent the generation of static electricity. d) Ionized air is recommended for discharge when handling CCD image sensor. e) For the shipment of mounted substrates, use boxes treated for prevention of static charges. 2) Notes on Handling CCD Cer-DIP Packages The following points should be observed when handling and installing cer-DIP packages. a) Remain within the following limits when applying static load to the ceramic portion of the package: (1) Compressive strength: 39N/surface (Do not apply load more than 0.7mm inside the outer perimeter of the glass portion.) (2) Shearing strength: 29N/surface (3) Tensile strength: 29N/surface (4) Torsional strength: 0.9Nm b) In addition, if a load is applied to the entire surface by a hard component, bending stress may be generated and the package may fracture, etc., depending on the flatness of the ceramic portion. Therefore, for installation, either use an elastic load, such as a spring plate, or an adhesive.
Upper ceramic layer 39N 29N 29N 0.9Nm
Lower ceramic layer
(1)
Low-melting glass
(2)
(3)
(4)
c) Be aware that any of the following can cause the glass to crack: because the upper and lower ceramic layers are shielded by low-melting glass, (1) Applying repetitive bending stress to the external leads. (2) Applying heat to the external leads for an extended period of time with soldering iron. (3) Rapid cooling or heating. (4) Rapid cooling or impact to a limited portion of the low-melting glass with a small-tipped tool such as tweezers. (5) Prying the upper or lower ceramic layers away at a support point of the low-melting glass. Note that the preceding notes should also be observed when removing a component from a board after it has already been soldered. 3) Soldering a) Make sure the package temperature does not exceed 80C. b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a grounded 30W soldering iron and solder each pin in less then 2 seconds. For repairs and remount, cool sufficiently. c) To dismount an imaging device, do not use a solder suction equipment. When using an electric desoldering tool, ground the controller. For the control system, use a zero cross type. - 11 -
ILX532A
4) Dust and dirt protection a) Operate in clean environments. b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity ionized air is recommended.) c) Clean with a cotton bud and ethyl alcohol if the glass surface is grease stained. Be careful not to scratch the glass. d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when moving to a room with great temperature differences. 5) Exposure to high temperatures or humidity will affect the characteristics. Accordingly avoid storage or usage in such conditions. 6) CCD image sensors are precise optical equipment that should not be subject to mechanical shocks.
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Package Outline
Unit: mm
28pin DIP (400mil)
71.000.8
28
22
21
15
5.00.5
H 8 14
0.25
1 68.0
4.00.5
1. The height from the bottom to the sensor surface is 2.4mm0.3. 2. The thickness of the cover glass is 0.8mm, and the refractive index is 1.5. 3. The notches of the package must not be used for reference of fixing.
PACKAGE STRUCTURE
PACKAGE MATERIAL
Cer-DIP
LEAD TREATMENT
TIN PLATING
LEAD MATERIAL
42 ALLOY
PACKAGE MASS
8.8g
DRAWING NUMBER
LS-C5(E)
ILX532A
4.400.5
2.54
16.5
16.5
0.46
3.60
(AT STAND OFF) 10.16
7
10.00.5
V
No. 1 Pixel
9.0
0 to 9
10.120.5
52.5(7mX7500pixels)
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